Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions

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" summary

Semidynamics builds an All‑in‑one RISC‑V block combining a 4‑way out‑of‑order core, RVV‑compliant vector unit (up to ~2k/4k‑bit lengths) and a shared‑register tensor unit that hits about 8 TOPS int peak but runs a small ML engine at ~1 TOP/core in real models. New ISA adds a single vector‑matrix multiply C = AB + C plus blrc load/store encodings to stream matrices. A special cache/miss engine sustains many outstanding misses (up to ~128 lines), yielding 75–80% tensor utilization* and real‑time throughput (~33 fps) on tested DL layers.

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" chapters (7)

1. 0:00Introduction
2. 2:55Single-block AI acceleration
3. 4:01Core and vector unit details
4. 5:07Tensor unit and new instructions
5. 7:37Memory bandwidth challenges
6. 8:40Performance results
7. 9:23Summary and All-in-one R550

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