RISC-V Instruction Set Explorer (RISE)

on YouTube ↗10m

" summary

University Demo Day demo of RISC-V Instruction Set Explorer (RISE) shows an in-house simulator that profiles binaries for basic block execution counts, per-instruction floating‑point rounding and NaN usage, min/max value ranges to decide 32 vs 64‑bit FP, and register/memory bandwidth stats (GUI displays JSON outputs). Simulator claims a 3× speedup over QEMU on MiBench/Whetstone. Tool performs automatic RISC-V customization from C and suggests custom instructions with measured cycle or instruction‑count reductions typically from 1% up to about 4%, with more improvements in progress.

AI-written summary · about

" chapters (5)

1. 0:00Introduction to RISE
2. 1:29Tool goals and challenges
3. 3:15Simulator speed and profiling
4. 5:21Graphical user interface demo
5. 7:28Q&A session

" related talks

• 17mDemo: RISC-V Models for Verification, Software Development and Architectural Explor...Larry Lapides · RISC-V Summit 2022
• 36mAccelerate RISC-V Instruction Set Simulation by Tiered JIT CompilationYen-Fu Chen, Ching-Chun (Jim) Huang, Meng-Hung Chen, Chia-Heng Tu · VMIL 2024
• 01h 10mWhy RISC-V Through ISA Customization DemonstrationKeith Graham · RISC-V Summit North America 2023
• 20mAnalysis for Code Size Opportunities in RISC VIbrahim Abu Kharmeh · RISC-V Forum: Developer Tools and Tool Chains 2021
• 15mCompared Analysis of GCC Codegen for AArch64 and RISC-VPaul-Antoine Arras · RISC-V Summit Europe 2025
• 01h 01mThe Genius of the RISC-V MicroprocessorErik Engheim · NDC TechTown 2021
• 01h 25mRISC V Bit Manipulation ISA Extension Spec, Hardware, SoftwareKen Dockser · RISC-V Summit 2019
• 02h 49mA Tour of the RISC V ISA Formal SpecificationRishiyur Nikhil · RISC-V Summit 2019