CHIPS Alliance: towards a unified open source ASIC design & DV workflow

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" summary

CHIPS Alliance consolidates six permissively licensed projects and shows concrete outputs: an SV-tools suite with SV-tests, Verible, Synlig and RISC‑V DV running daily CI; active work to add UVM-style verification to Verilator, clickable waveform↔code navigation, and open coverage collection; a Veer family of cores (EH1, EH2, EO2) used in the Guinevere example SoC generated by TopWrap with YAML descriptions, FuseSoC dependency handling, Renode co‑simulation, automatic bus bridging and CDC/width converters. Meetings run biweekly.

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" chapters (7)

1. 0:00CHIPS Alliance intro
2. 1:28CHIPS Alliance projects
3. 2:53SV Tools updates
4. 6:45Veer CPU cores
5. 10:12Guinevere SoC example
6. 13:45How to get involved with CHIPS Alliance
7. 14:38Q&A

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