Erbium SOC, Architecture, Design and Verification
summary
Erbium is a taped‑out, open‑source 8C16T RISC-V SOC with Vector and Tensor extensions, a per‑core L1 scratchpad and 16 MB MRAM, aimed at EdgeAI; the project publishes RTL, SystemVerilog/CocoTB VIPs, a makefile‑ready testbench, and an XSPI to AXI target implementation. Tooling work includes Surfer waveform fixes, BlueSpec compiler labels, a Peak RDL plugin, a language server and RAL output. Emulation runs as a C co‑sim today, FPGA‑synthesizable cores and a roadmap to tileable parts are being developed. The ET1000 (1,000 cores, 2,000 threads) exists at 5 nm and 40 W.
AI-written summary · about
chapters (12)
- 0:00Introduction and mission
- 1:10Open hardware philosophy
- 1:50Chip development roadmap
- 3:24Community tools and IP
- 6:01CPU architecture details
- 6:19XSPI and waveform debugging
- 8:36State machine optimization
- 9:08PeakRDL and workflow tools
- 11:12Register interface design
- 11:29Testing frameworks
- 11:53Q&A session
- 12:28Final discussion and wrap-up
related talks
20mRISC V and Chips Alliance Address new Compute Requirements
30mUnleashing Innovation from Core to the Edge
18mOpen Source computer architecture research at the BSC
45mProcessor IP Showcase
08mTenstorrent: Extending the RISC-V Open Source Ecosystem
16mThe Future of Ibex - A Production-grade, Open Source 32-bit RISC-V Core
24mEuropean Processor Initiative
18mNuclei: Full-Spectrum RISC-V IP & Automated SoC Design from Months to Hours