Unleashing Innovation from Core to the Edge

on YouTube ↗30m

" summary

Western Digital open-sources a RISC‑V core called swerve core (32‑bit RTL in SystemVerilog) plus an instruction‑set simulator (32/64‑bit) on GitHub, and prototypes an Omni‑Extend fabric — a cache‑coherent memory fabric riding on Ethernet PHYs using a Barefoot Tofino switch programmed in P4. The custom core reports ~50% higher coremark/MHz, ~30% smaller silicon area and ~30% lower power versus prior in‑house designs, and the effort targets billions of embedded cores per year.

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" chapters (9)

1. 0:00Start
2. 7:01From General Purpose to Purpose Built
3. 11:42Western Digital Proposes Open Standard
4. 14:26Let's standardize a Cache Coherency Fabric
5. 16:56Introducing Western Digital's RISC-V Core
6. 18:04Core Mark/Mhz Performance
7. 21:47Challenge-Open Source is New to Hardware
8. 24:30Western Digital Swe RV Instruction Set Simulator (ISS)
9. 25:17Summary

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