UltraSoC

on YouTube ↗02m

" summary

Demo shows an FPGA with two ARM cores and a RISC‑V core running UltraSoC live monitoring and a new chip analytics suite that uses ML-based analytics to surface faults and speed root cause search. Announced full Swerve support for debug and trace and claims compatibility with other RISC‑V standard cores. Also won an award for a universal lockstep monitor intended to enable automotive and safety‑critical use, presented as working on the demo system.

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