SiFive Presentation
summary
Claim: go from a custom RISC-V CPU to hello world in 30 minutes by using a web flow that configures and generates actual deliverables. Configure a core in SiFive Core Designer to produce RTL, documentation, software BSP and an FPGA bitstream for Digilent Arty and other supported boards, download the deliverables (currently a 19 gigabyte download to flash via the Xilinx tool referenced), program the FPGA, then build and load the example with Freedom Studio / Freedom II SDK to get serial console output.
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chapters (8)
- 0:00Introduction to SiFive
- 1:30Hardware development challenges
- 3:15SiFive Core Designer overview
- 5:05SiFive RISC-V IP portfolio
- 7:00Configuring a custom CPU core
- 8:55Downloading FPGA deliverables
- 10:25Programming FPGA and running Hello World
- 11:45Q&A and demos
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