Software Flow for Complex SoC FPGA
summary
Describes a software flow that ties a configurable FPGA fabric to a RISC-V SoC using a GUI-driven configurator that emits XML metadata, auto-generates C headers for register and DDR settings, and enforces pin and clock rules. Boot differs: ROM stage is replaceable with MIT-licensed source so processors are controllable from reset; contexts use PMPs to separate memory/interrupt maps. Toolchain components named include SoftConsole, Libero IDE and the Renaud simulator for hardware-less testing and CI.
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chapters (15)
- 0:00Introduction
- 0:37What is SoC FPGA
- 1:21FPGA Refresher
- 2:10FPGA IO
- 2:58FPGA Programming
- 4:01Associate FPGA
- 4:40FPGA
- 4:58SOC VGA
- 5:27MDMA
- 5:52System Start Up
- 8:15Bootloader
- 9:47Memory Protection
- 14:49SOC Configurator
- 17:42Under the hood
- 19:38Resources
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