Prototyping RISC V Based Heterogeneous Systems on Chip with the ESP Platform
summary
The ESP open-source platform lets teams assemble heterogeneous RISC-V SoCs by composing RISC-V cores, accelerator tiles and a distributed network-on-chip with 1–4 memory tiles and coherent caches, using multiple design flows and synthesis backends. It boots Linux without special kernel patches, generates device-driver and platform templates, and supports push-button FPGA prototyping to validate end-to-end hardware/software stacks. The project reflects over seven years of work and includes an NVIDIA accelerator integration demonstration.
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chapters (14)
- 0:00Introduction to ESP platform
- 1:27Challenges in heterogeneous SoC design
- 3:21ESP architecture and design flow
- 6:34Memory coherence and software integration
- 9:04Tile-based system and platform services
- 12:15Tile configuration and runtime services
- 15:08Design automation and rapid prototyping
- 17:39Prototyping interface and configuration
- 20:16Network-on-chip and topology choices
- 23:37Memory tiles and system integration
- 25:46Performance estimation and experimentation
- 27:17Prototyping in the cloud and testing
- 28:26Hardware-software interface simplification
- 30:12Q&A and conclusion
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