RISC V in Practical Education of Computer Architecture
summary
Course uses Spike and Venus plus gem5 and real RTL from IBEX, Arianna and BOOM to move students from assembly to microarchitecture. A Python pipeline viewer (pip install pipeline viewer) parses DPI traces into a common trace format so students measure IPC, inspect branch predictor updates, and visualize instruction lifecycles without poring over waveforms. RTL testbenches already emit traces; FPGA export via Open SoC Debug is planned for Spring 2020 to run longer experiments on hardware.
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