Open Source Processor IP for High Volume Production SoCs CORE V Family
summary
OpenHW Group commits to produce production-grade CORE-V cores and tape out a submicron SoC by end of 2020 using NXP’s donated i.MX as the non‑open peripheral platform, integrating cv64 (Ariane) and cv32e (CORE-V), verified on commercial SystemVerilog flows with testbenches hosted in IBM cloud. Verification infrastructure and stimuli are open; formal runs by OneSpin surface 13 issues so far. Goal targets real silicon evaluation boards and Linux/software bringup.
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chapters (14)
- 0:00Start
- 1:31Outline
- 3:26Barriers to adoption of open-source IP
- 4:11RISC-V ISA Brings Open Source Paradigm to CPU Design
- 5:24Many RISC-V Open Source Cores... ...and counting...
- 8:31OPENHW Partners
- 9:06CORE-V Family of RISC-V Cores
- 10:00CORE-V Proven Processor IP
- 10:35OpenHW Group Board of Directors • Xiaoning Qi, Alibaba Group
- 10:50Working Groups & Task Groups • Board appoints Chairs of ad-hoc working groups and has final approval of working group recommendations ⚫Technical Working Group and Marketing Working Group will be
- 13:42CORE-V Chassis SOC Ecosystem
- 14:22CORE-V Chassis - Call for Participation
- 16:14NXO & OPENHW Driving Open Source RISC-V Adoption
- 16:25Formal Verification of RISC-V Cores
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