An Open-Source CVA6S+ High-Performance, Cache-Coherent Cluster for 64b Automotive MPUs

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" summary

An open-source CVA6S+ cluster implements AMBA 4 ACE coherence with a new CCU IP and a snoop fabric using snoop-based MOESI to move dirty L1 lines, targeting 64b automotive MPUs. Prototype integrates CV32E40P cores and HPD caches on a Cheshire SoC (VCU128 FPGA, GF 12nm for ASIC figures). Results show 1.8× SPLASH-3 speedup vs single core, 25% gain over the previous CV6/write-back design, and a CCU cost of about 35 kGE.

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" chapters (10)

1. 0:00Introduction and motivation
2. 1:47Open source gap in MPUs
3. 3:11Calista’s cluster design
4. 3:53CV32E40P core optimizations
5. 7:27HPD cache coherent support
6. 8:31Cache Coherence Unit (CCU)
7. 9:14Evaluation setup and benchmarks
8. 10:38Performance results
9. 11:40Area overhead analysis
10. 12:46Conclusion and future work

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