CPU Utilization Counters for RISC-V
summary
Proposal adds two CSRs: a core-cycle counter that increments at actual CPU frequency and an active-time counter that ticks at a fixed reference rate, both stop in idle. The OS computes current frequency as the delta ratio of those counters times reference_freq and derives a normalized utilization without traps or IPC. Implementation exists in Linux kernel branch, OpenSBI and a hardware platform; benchmarks show negligible performance loss and about 62% energy reduction versus a performance-only policy. Hardware cost is two 64-bit counters and no scheduler rework beyond CSR reads.
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chapters (9)
- 0:00Introduction
- 1:01Problem with CPU utilization
- 3:32Linux kernel and DVFS
- 6:06RISC-V current gap
- 7:53Proposed counters solution
- 9:20Why not reuse existing counters
- 11:29Benchmark results
- 13:16Why this fits RISC-V
- 14:20Impact and conclusion
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