Ultra Low Power RISC-V Core Retention with Warm Restart Extension
summary
SXP5 RISC‑V core adds a retention domain and a tightly coupled retention stack in TCM plus a retention request protocol to save full CPU context and CSRs including hardware‑updated read‑only registers, then perform a warm restart from a captured entry sequence. A tiny custom XSTP extension of two instructions drives low‑latency microops that write/read the stack, recovery for some CSRs costs <10 instructions, hardware overhead is <3 logic gates plus stack area, and verification includes thousands of random tests and formal checks with 100% RTL coverage.
AI-written summary · about
chapters (6)
- 0:00Introduction
- 1:44State retention problem
- 3:59New retention approach
- 6:45Warm restart process
- 9:41Results and benefits
- 12:12Q&A
related talks
12mRetargeting a legacy ISA CPU core to the RISC-V architecture
21mAdaptable, Scalable and Predictable Computing with a Multi-threaded RISC-V Architectu...
15mOptimizing Real-Time Application Requirements on ARC-V Processors Leveraging RISC-V Ex...
19mEnhancing RISC-V Embedded Processor Performance Through Advanced Instruction F...
20mCould RISC-V Become a Force in HPC?
21mRISC-V Nested Virtualization
14mExtending RISC-V with SCAIE-V
43mRISC-V CPU Project in Western Digital