SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification
summary
Claims a synthesizable reference model that moves the golden ISA into hardware, generated by a semantic migration tool from Spike to chisel primitives, and integrated with divtest. It uses speculative execution using DUT commits and reuses DUT cache blocks to cut memory traffic. Prototype targets emulators/IPJs and reaches about 60 MHz on FPGA, roughly 10× faster than prior co‑simulation; prior RTL+host co‑simulation fell below 1 MHz on a Platinum board.
AI-written summary · about
chapters (9)
- 0:00Introduction
- 0:47Verification challenges
- 3:20Limitations of co-simulation
- 5:25Synthesizable verification method
- 6:10Hardware reference model efficiency
- 9:21Cache system optimization
- 11:12Reference model correctness
- 12:37Simulation speed results
- 13:19Q&A session
related talks
13mIntroduction to RISC-V Processor Verification
24mRISC V Processor Verification based on Open source Framework
23mOpen Source Verification Platform for RISC V Processors
46mRISC-V Open ISA’s Shock Wave of Processor Innovation Causing Seismic Shift
15mThe RISC-V Verification Ecosystem with Open Standards and Commercial Tools
23mThe Continuum of RISC-V Compliance and Verification Testing
19mThe role of software in validating silicon IP
12mRISC-V: Hardcore/Softcore Co-Simulation Environment with Cycle-Accurate Rollback