SafeRV Building Blocks for Safety Critical RISC V Systems
summary
SafeRV presents concrete RISC-V building blocks: a silicon-proven Shakti C-class core extended with 29 performance counters, CSRs reorganized into seven daisy chains to avoid critical-path penalties, ECC on GPRs pipelines and caches, TLB single/double error detection, and configurable tightly integrated memories (e.g. 16KB cache + 8–16KB scratchpad). Proteges generates Bluespec cache-coherence (MSI/MESI/MOSI) controllers, NoC implements high/low criticality arbitration (Garnett 2.0) and a debug v-net, triple modular redundancy exists for functional units, much code is open-source BSD, and hypervisor/NOC determinism work is still in progress.
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chapters (10)
- 0:00Introduction to SafeRV
- 8:11Safety vs security differences
- 10:16Building blocks and optimizations
- 13:29CSR daisy-chaining for counters
- 15:37Tightly integrated memories
- 17:21Custom CSRs and interrupts
- 18:50Cache coherence with Proteus
- 20:16ECC and fault tolerance
- 20:40Network-on-chip determinism
- 22:29Open source and Q&A