SweRV Cores Roadmap
summary
Roadmap describes two SweRV second‑generation cores: a tiny L2 aimed at minimal area and one‑IPC from local memories — measured at 0.023 mm² (TSMC 16nm) with CoreMark ~3.6 @600 MHz — and an H2 SMT core that adds a second hardware thread for high throughput, non‑blocking divides, zero‑cycle BTB and fast interrupt paths, pipelined DMA, and only ~5–10% area overhead for threading; single‑thread CoreMark ~4.9 and 6.5 CoreMark/MHz with two threads, with SMT giving ~1.9× average speedup and sources released via CHIPS Alliance.
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