Introduction to SoC+FPGA
summary
Single-chip SoC+FPGA boards boot Linux with vendor toolchains (Quartus, Vivado, Libero) to generate HDF/QTS/BSP files, then use upstream U-Boot and the mainline FPGA manager to program bitstreams; small kits exist (~$10) while development boards can be ~$125. FPGAs run hundreds of MHz, expose hundreds–thousands of I/Os, and support partial reconfiguration. Runtime wiring uses Device Tree overlays to create devices and bind drivers, but unloading overlays leaves the FPGA programmed. Overall, prefer loading and managing the FPGA from Linux rather than from U-Boot.
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chapters (28)
- 0:00Introduction
- 0:10About me
- 0:53Agenda
- 1:27What is an SoC
- 4:47Schematic of an FPGA
- 7:30Why FPGA
- 8:56Questions
- 9:29Cypress Devices
- 10:33Open Source Tools
- 11:30Schematics
- 11:48BSP
- 12:08MicroSemi Smart Fusion
- 14:15Cortex A9
- 15:35Quartus
- 18:53Silence
- 21:04Vivaro
- 21:41Bootloader
- 22:42Linux support
- 23:35How to boot
- 28:27Vendor interfaces
- 29:06Device 3 overlays
- 29:39Demo
- 30:40RS3 Overlay Source
- 31:13FPGA Manager
- 32:10How does it work
- 33:24FPGA Manager Demo
- 34:08Conclusion
- 34:36Loading sequence
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