An Introduction to SPI-NOR Subsystem
summary
Introduces the SPI-NOR subsystem that sits in MTD and the m25p80 translation layer, explains how controllers register flash via spi_nor_scan and expose opcodes, address bytes and dummy cycles, and shows concrete performance: traditional SPI reads ≈ 800 KB/s at 70% CPU, memory‑mapped SPI-NOR ≈ 4 MB/s and DMA paths reach ≈20 MB/s at 15% CPU. Covers support for SPI/QSPI/OSPI, SFDP (1.6), 4‑byte addressing, octal/DTR work, and ongoing gap: lack of generic DMA/bounce‑buffer handling.
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chapters (17)
- 0:00Intro
- 0:36What's in the presentation?
- 1:02What is a SPI-NOR Flash?
- 1:35Why SPI-NOR flash?
- 3:25Typical SPI-NOR flash
- 5:18SPI-NOR Flash Hardware
- 6:33Communication Protocol
- 8:06Types of Controllers
- 11:59Traditional SPI Controller
- 14:12Accessing flash via SPI framework
- 19:26Accessing flash via SPI-NOR framework
- 19:57Specialized SPI controller-MMIO Interface
- 22:21Where to put your driver?
- 24:01Writing a SPI-NOR controller driver
- 30:29Performance Comparison
- 38:43Adding DMA support
- 41:23References
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