Introduction to HyperBus Memory Devices
Talkat Open Source Summit Europe + Embedded Linux Conference Europe 2019 · on Tuesday, 2019-10-29· at 11:30· Forum 1·
summary
HyperBus is an 8‑line DDR memory bus delivering about 400 MB/s at 100–200 MHz by transferring 16 bits per clock; HyperFlash is a NOR CFI device with 512‑byte internal buffering and 16‑byte ECC granularity. Linux merged a HyperBus framework in kernel 5.3 that reuses the CFI command‑set but changes status polling to read a status register. Controller drivers must implement five ops (read16, write16, copy_from, copy_to, calibrate), register devices via hyper_bus_register_device, and address DMA and 16‑bit write granularity for acceptable performance.
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chapters (24)
- 0:00Intro
- 0:33What's in the presentation?
- 0:57What's HyperBus?
- 2:04HyperBus Memory Devices
- 4:26HyperRAM
- 5:19Phases of a transaction
- 6:08Communication Protocol
- 6:42Command Address (CA) Bits
- 10:09Write Programming Sequence
- 11:45Address space overlays (ASOs)
- 13:07Types of HyperBus Memory Controllers (HBMC)
- 14:06MMIO capable controllers
- 15:29Kernel support for HyperFlash
- 18:15Writing a HBMC driver
- 18:35hyperbus ops
- 21:12Registering Device
- 22:18Device Tree representation
- 23:29Accessing from user space
- 24:09HyperFlash and SPI
- 25:11Comparison to traditional SPI flash protocol
- 26:19XSPI compliant HyperFlash
- 27:48Extending spl-mem for HyperFlash
- 29:04Future Enhancements
- 32:33References
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