Leveraging Scala to Build Hardware at Scale
summary
SiFive describes a full chip stack written in Scala: Chisel as the hardware construction DSL, the Diplomacy parameter framework and FIRRTL as the compiler that lowers to Verilog, claiming a complex modern SoC can be expressed in <30 lines of statically type‑checked Scala. They taped out a FU540/RV64 quad core at 1.5 GHz in 28 nm, put it on an 8 GB dev board running Debian and YOLOv3 via an FPGA ML accelerator, and offer a web service to configure cores and drive synthesis to fabrication.
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chapters (11)
- 0:00Introduction and motivation
- 6:48Trends in hardware industry
- 11:30RISC-V and open-source ISA
- 15:14Demo of hardware board
- 19:33Chisel and hardware abstraction
- 26:40Fertile compiler and transformations
- 29:06Web services for hardware design
- 31:12Industry adoption of RISC-V
- 33:09Why Scala for hardware
- 35:21Future of open hardware ecosystem
- 37:13Q&A on debugging and ecosystem
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