Open Hardware: Skyrocketing Momentum & Global Adoption from Embedded to Enterprise
summary
RISC-V claims rapid real-world traction: industry research updates the projection to 80 billion RISC‑V cores by 2025, and about 23% of new ASICs already include a RISC‑V core. Open hardware pieces exist now — Western Digital’s Swerve open cores on GitHub run Linux — and core specs (vector, crypto, hypervisor, PMP) follow a 45‑day public review before ratification. Tooling and programs include Buildbot CI for RISC‑V Labs, free developer boards that require upstream contributions, and fast ports of libraries like DPDK/SPDK. Training sees 6,000+ course signups and 2,200 members across 70 countries.
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chapters (25)
- 0:00Introduction
- 1:59Risk5 Architecture
- 2:38Modular Architecture
- 3:24Opportunity
- 5:21Overall
- 8:09IoT
- 9:05Where are we
- 10:41Alibaba
- 11:10Android SIG
- 11:48Automotive
- 12:35IoT Devices
- 13:22AI ML
- 13:53Edge Computing
- 15:46Risk 5 International
- 17:56Risk 5 Innovation
- 21:26Specifications
- 23:15Innovation
- 24:32Technical Programs
- 28:20Porting
- 29:13Open Source Ecosystem
- 30:08Challenge
- 30:33Visibility
- 31:25Risk 5 Approach
- 33:11Risk 5 Lab
- 35:36Risk 5 in Data Centers
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