Host Performance Booster (HPB): Introduction and Current Mainline Support Status
summary
Host Performance Booster (HPB) caches UFS logical-to-physical mappings in host RAM so the device skips slow NAND map reads, claiming much lower read latency and higher sustained throughput. Implementation follows JEDEC UFS HP spec and uses per-region/subregion state with LRU and pinned regions, and a 128 GB device with 4 KB blocks requires roughly 128 GB → ~256 MB mapping if fully cached. Linux mainline accepts the series (patch set ~v40, HP 2.3 support) and benchmarks show big gains on large IO ranges and small-chunk reads.
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chapters (19)
- 0:00Intro
- 0:29Agenda
- 1:18What is UFS?
- 1:51Performance: eMMC vs UFS • Performance Comparison with eMMC
- 2:50Architectural Overview
- 4:25UFS Subsystem
- 5:17Transactions in UFS
- 6:36Scope of Improvement: The Read Latency
- 10:18What is HPB?
- 10:59Concept of HPB
- 15:38Overall Behavior
- 21:18Data Structure
- 23:58State change of HPB
- 29:30Region Management
- 38:40Benchmark & UX experience
- 40:43Chunk-Range Result
- 42:22HPB Linux Upstream Status
- 43:37Timeline
- 44:44Conclusion
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