Simulating Partial Reconfiguration in cocotb via Multi-Process DPI Barriers
summary
Claims a working multi-process per-module simulator that lets cocotb and Verilator run a full RTL sim while swapping modules at runtime without recompilation. Uses SystemVerilog DPI wrappers, shared memory inbox/outbox channels, and a lock-free sense-reversing barrier per clock to synchronize processes every cycle. Swaps are OS process replace: kill old, start new, resume barrier. VPI state, Python objects, and test flow remain unchanged and no cocotb or Verilator code is modified.
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chapters (10)
- 0:00Introduction to partial reconfiguration simulation
- 1:24What partial reconfiguration enables
- 2:48Challenges in RTL simulator module swapping
- 3:54VPI and DPI frameworks in cocotb
- 6:01Pink PR framework overview
- 7:24Traditional PR simulation limitations
- 9:07Multi-process DPI barrier approach
- 11:13Three-phase synchronization in barriers
- 13:19YAML configuration and test setup
- 14:24Solution summary and Q&A
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