Open source design testing and verification with UVM and Verilator

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" summary

Verilator now supports many non‑synthesizable SystemVerilog features enabling near‑complete UVM use: full class hierarchy and parameter resolution for UVM (all but ~40 lines of a 36,000‑line codebase), fork/process semantics and STD process support, and constrained randomization proof‑of‑concept using the Crave backend. Work reduces verilator compilation memory by about 11% and speeds up elaboration up to 19% in spots; parameterized classes and fork local fixes are implemented and the UVM hierarchy compiles with verilator.

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" chapters (11)

1. 0:00Open source verification with UVM
2. 1:06Verilator overview and advantages
3. 2:50Timing constructs for UVM in Verilator
4. 4:37Fork processes and variable access
5. 6:23SystemVerilog process management
6. 7:50Parameterized classes for UVM
7. 9:59SystemVerilog features and randomization
8. 11:42UVM compatibility progress
9. 13:34Verilator compilation optimizations
10. 15:46Parallel compilation efforts
11. 16:48Q&A

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