Data transport in a radio telescope: Remote Direct Memory Access over Ethernet from FPGA to GPU
summary
Radio telescope front ends stream huge continuous bursts of samples and the bottleneck is moving that traffic straight into GPU memory. Implementation of RoCE v2 RDMA from FPGA to GPU aims to bypass kernel copies and the CPU so a single server can exceed the usual 40 Gbps receive limit and cut system power. Current work uses Xilinx Alveo for development with an Intel Agilex board planned, VHCL components simulated, and a right only operation implemented in FPGA firmware; firmware will be released open source. Goals scale from current 3–10 Gbps stations toward 400 GbE / terabit-class links.
AI-written summary · about
chapters (5)
- 0:00Radio astronomy data transport
- 6:46Front-end to processing pipeline
- 12:24High-speed transport challenges
- 18:47RDMA over Ethernet progress
- 20:14Q&A on clock sync
related talks
27mGNU Radio in a Direct-RF World
31mData Streaming from SDR to Servers for Cognitive Radar and EW
19mProgramming the Electromagnetic Spectrum
32mFrom UART to PCIe and DMA: Selecting Connectivity for Your FPGA-based Subsystem
19mThe Future of Digital RFICs
32mSponsor Talk – Haydn Nelson
29mAnalog Devices: Implementing OFDM Radar & DOA on DirectRF Platforms using IIO and GNURadio
27mEnabling Performance Portability of GNU Radio on Heterogeneous Systems