Effective Timekeeping in RISC-V Processors: Overview of mtime Design Approaches

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" summary

RISC-V’s 64-bit mtime is memory-mapped but can be implemented four practical ways: trap-emulate CSR accesses (used by Ibex and NewRISC32) which is simple but slow; a dedicated 64-bit wire for low-latency access which costs area; let CSR instructions issue loads/stores via the memory stage introducing potential stalls; or use a CSR-based mtime where mtime is a shadow of mcycle (as in Rocket Chip) to save area and speed accesses for single-clock deeply embedded cores.

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" chapters (14)

1. 0:00mtime in RISC-V
2. 1:03What is mtime
3. 4:13Memory-mapped mtime registers
4. 6:46mtime access design approaches
5. 8:52Emulating mtime via software
6. 9:56Direct mtime signal routing
7. 10:59CSR-to-bus mtime translation
8. 12:28Pure CSR mtime design
9. 13:56Shadow CSR for mtime
10. 14:17mtime design trade-offs
11. 14:38Q&A on RISC-V cores
12. 17:06Hard real-time mtime design
13. 18:51mtime optimizations and size
14. 20:17CSRs vs memory-mapped mtime

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