Blackwire: WireGuard in HDL at 100+ Gbit/s

on YouTube ↗22m

" summary

Blackwire implements WireGuard as HDL/RTL for FPGA NICs and reaches 100 Gbits/s on the data path while keeping control on a RISC‑V core; the project is about 75% complete and open source. The design uses a triple‑session memory scheme to atomically switch handshakes without dropping packets, budgets ~58 ms per handshake for 1k peers, and keeps the fast path in RTL. The allowed IP lookup uses a pipelined sparse binary‑tree algorithm ported to SpinalHDL yielding ~800M lookups/sec and ~1 µs latency.

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" chapters (14)

1. 0:00Introduction
2. 1:05WireGuard core features
3. 3:30WireGuard on FPGA
4. 5:15Hardware challenges
5. 6:37100 Gbit/s architecture
6. 8:01RISC-V core choice
7. 10:14WireGuard with SpinalHDL
8. 12:44IP lookup optimization
9. 14:48Open-source status
10. 16:12Q&A: Handshake & UDP
11. 17:14Q&A: LiteX & Corundum
12. 18:37Q&A: SpinalHDL vs Verilog
13. 20:04Q&A: 100 Gbit/s testing
14. 21:10Q&A: SpinalHDL pain points

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