Bluespec is my favourite HDL and here's why
summary
Bluespec HDL is presented through a concrete OpenMPW toy project that compiles to Verilog and runs under BlueSim simulation showing a GCD example and a free-stage pipeline that multiplies values. The compiler enforces an advanced type system with tagged unions, polymorphism and monads, provides battle-tested FIFOs, CDC and an FSM generator, and produces high-performance RTL. Integration requires manual Verilog glue, public docs and community are sparse, and the showcased RISC-like CPU is about 200 lines of Bluespec.
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