Modular Hardware Design of Pipelined Circuits with Hazards

on YouTube ↗19m

" summary

Proposes hazard interfaces that generalize valid-ready by carrying arbitrary “reserve” values and a ready function, plus map-reduce style combinators that decompose cross-stage control. Implements a compiler that emits synthesizable Verilog and a type checker that proves absence of combinational loops. Evaluates on a 5‑stage RISC‑V core (CPI unchanged, lower area and power but lower max freq) and a 100 Gbps NIC (≈6% more LUTs, ≈3% fewer FFs, <2% throughput loss).

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" chapters (9)

1. 0:00Modular hardware design
2. 1:04Combinator-based design
3. 3:16Limitations in pipeline circuits
4. 5:24Structural hazards with valid-ready
5. 7:34Data and control hazard interfaces
6. 10:07Hazard interface for pipelines
7. 12:14Case studies and results
8. 14:23Key contributions
9. 15:04Q&A

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