RISC-V Instruction Set Extensions for Cryptography - From Research to Standardization

on YouTube ↗16m

" summary

RISC‑V already includes scalar crypto extensions ratified 2021 covering bit ops, carry‑less multiply, AES and SHA and data‑independent execution; AES instructions add roughly 1000 gate equivalents and give multi‑x speedups versus pure ISA sequences. Vector crypto proposals are in public review and Ascon (the Ascon winner) maps to just two extra ops with a smaller memory footprint, while fully hardwired accelerators blow up area to >4000 gate equivalents and can reach ~50× speedups.

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" chapters (11)

1. 0:00RISC-V crypto extensions intro
2. 1:24Crypto algorithm standardization timeline
3. 2:51Adoption challenges in crypto support
4. 3:53Ratified crypto extensions overview
5. 5:16AES instructions integration
6. 7:06Planned vector crypto extensions
7. 7:48Lightweight crypto and Ascon
8. 9:38Hardware impact: Ascon vs AES
9. 11:02Parallel Ascon case study
10. 12:46Physical attack countermeasures
11. 13:28Future challenges

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