On the Efficiency of RISC-V Cryptographic Instruction Set Extensions
summary
Implements 11 algorithms (eight block ciphers, three hashes) as integer-only and integer+crypto ISAs, synthesizes supporting hardware into a 5-stage RV32 core and measures code size and cycles. Baseline core is ~19k gates and adding crypto plus bit-manipulation costs ~+8k gates, with AES/SHA-specific ops accounting for ~5.7k gates. AES and SHA-256/512 see very large cycle reductions, many lightweight ciphers see negligible wins, and a proposed matrix-manipulation micro-op set yields big speedups for permutation-heavy ciphers at roughly +800 gates and two extra reg slots.
AI-written summary · about
chapters (10)
- 0:00Introduction to talk
- 0:21Outline and methodology
- 1:24Crypto instruction set overview
- 4:13Implemented algorithms explained
- 9:13Software implementation highlights
- 11:19Performance comparison results
- 12:27Hardware implementation details
- 14:53Area and efficiency analysis
- 16:39Alternative instruction proposals
- 18:46Future work and conclusions
related talks
16mRISC-V Instruction Set Extensions for Cryptography - From Research to Standardization
14mUsing Proposed Vector And Crypto Extensions For Fast And Secure Boot
19mAn Open Source Approach to System Security
13mUsing RISC V As a Security Processor For DARPA CHIPS And Commercial IoT
14mSecurity Task Group Update And RISC V security Extension
20mRISC-V open designs and contributions to hardware security research and development activities
18mCPU Security in the Context of RISC-V
40mImplementation