RISC-V Forum: Security 2021
2021-04-14
-- online --
| title | author | length |
|---|---|---|
| OpenSBI Domain Support | Anup Patel | 30m |
OpenSBI adds domain support in v0.9 to provide system-level partitioning by using RISC-V physical memory protection (PMP) and a domain model that can extend to… | ||
| Information Flow Confidentiality and Integrity on a Rocket RISC-V SoC | Gregory Sullivan | 26m |
Dover implements per-word, per-instruction taint tracking in hardware on a Rocket RISC-V SoC, grabbing runtime instruction trace and mapping RISC‑V ops to… | ||
| Extending Security to Resource Constrained Devices | Kate Stewart | 10m |
Zephyr RTOS aims to bring audited security to constrained devices, started five years ago and now supporting RISC‑V 32/64 with over 250+ boards (about 8 RISC‑V… | ||
| Using PMP, ePMP and Rust to Protect Embedded Kernels, Even from Themselves | Alistair Francis | 16m |
Demonstrates that Tock OS uses RISC-V PMP write-xor-execute to mark kernel stack/data non-executable and kernel text read-only, and that ePMP default-deny adds… | ||
| Lightning Talk: A Trusted OS for RISC-V ? OP-TEE is a Candidate | Marouene Boubakri | 10m |
Claims a working port of OP-TEE on RISC-V that boots via U-Boot, loads openSBI, runs OP-TEE in S-mode and Linux in the rich world, and executes a trusted… | ||
| RISC-V Based Secure Flight Computer System | Shreekant Thakkar | 16m |
Project builds a RISC-V flight SoC called Falcon SoC to replace Pixhawk FMUv6x stacks, targeting one order of magnitude better performance and efficiency for… | ||
| Lightning Talk: What in RISC-V IOPMP | Shan-Chyun Ku | 10m |
IOPMP defines access control for non‑RISC‑V bus masters (DMA, NICs) by mapping source IDs to memory domains (MDID) and checking permissions via a searchable… | ||
| Trusted RV: Trusted Execution Environment, Secure Coprocessor, and their Program... | Kuniyasu Suzaki | 16m |
A RISC-V prototype combines four 64-bit application cores and one 32-bit Secure Unit that runs Zephyr RTOS and holds device keys and certificates as a root of… | ||
| Lightning Talk: Timesecbench: A Work in Progress Benchmark Suite to Assess Timing... | Ronan Lashermes | 08m |
timesecbench is a portable microarchitectural timing-leakage benchmark suite implemented for RISC‑V cores that currently supplies four benchmarks targeting L1… | ||
| On the Efficiency of RISC-V Cryptographic Instruction Set Extensions | Tolga Yalcin, Gorkem Nisanci | 19m |
Implements 11 algorithms (eight block ciphers, three hashes) as integer-only and integer+crypto ISAs, synthesizes supporting hardware into a 5-stage RV32 core… | ||
| RISC-V International Security Overview | Helena Handschuh | 21m |
RISC-V International publishes a stable crypto extension (crypto version 0.8.1) that adds small scalar instructions plus AES/SHA/SM3/SM4 accelerators and an… | ||
| RISC-V Welcome | Kim McMahon | 03m |
Short welcome and program overview for the RISC-V Forum: Security 2021 with logistics and sponsorship details. Event format uses short-form, single-topic… | ||
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