spinal.lib.bus.tilelink : An Tilelink interconnect generator based on fiber
summary
A Tilelink interconnect generator implemented in SpinalHDL uses fiber-based negotiation (user-space elaboration threads) to propagate and mutate parameters across nodes without a centralized scheduler, auto-inserting arbiters, decoders and automatic adapter insertion for mismatched bus widths, and supporting the coherent probe channels for memory coherence. It negotiates IDs, address widths and data-bus sizes at elaboration time, targets multicore RISC-V (32/64-bit) systems, runs Linux/Debian on a Nexus5 demo (Doom shown), and offers decentralized elaboration to keep top-level code small; L2 cache work is forthcoming.
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chapters (6)
- 0:00Introduction
- 3:15Hardware description libraries
- 7:10Parameter propagation
- 10:02TileLink interconnect
- 12:33Related projects Nexus 5 rvls
- 15:26Q&A
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