Next big step for Verilator: towards four-state logic and UVM compatibility
summary
UVM 2017 and UVM 2020 compile with Verilator and nearly 100 pull requests land for scheduling (eager triggers, three‑stage scheduling, immediate finish), concurrent assertions, and an IEEE‑compliant force/release overhaul that now handles conditional and overlapping forces, unpacked types and reals. A feature‑flagged four‑state prototype encodes values as two bitvectors per signal (binary + XZ), first PR supports arithmetic on 1‑D signals and simulates the I3C core; expect slower runtime and ongoing SV‑tests dashboard tracking.
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chapters (9)
- 0:00Verilator’s next steps
- 0:41UVM compatibility progress
- 2:05Dynamic scheduling improvements
- 5:36Force/release in IEEE compliance
- 7:40Four-state logic development
- 9:06Testing four-state logic
- 10:09Encoding four-state logic
- 13:23SystemVerilog test progress
- 14:30Q&A on UVM trade-offs
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