3 Talks for the Price of 1!
summary
Built an open SystemVerilog acid test suite that exposes what each parser and tool actually implements, then absorbs new parsers (Google’s verible-based linter, a Cordelia/antlR parser, a tree-sitter grammar and a Rust parser) with one unexpected PR becoming the most green. Created a UHDM universal model so different front ends can interoperate. Demonstrates cocotb USB 1.1 compliance testing across simulators and claims VexRiscv uses one third of the FPGA resources compared with a common commercial softcore.
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chapters (11)
- 0:00Intro
- 4:25SystemVeryLog Test Suite
- 6:40Parsers
- 9:02SystemVeryLog
- 12:22OSIS
- 12:36VHDL
- 12:49Verilog
- 14:22Cores
- 16:52Open Source
- 18:26Tools
- 23:50Documentation
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