The Evolution of Memory Technologies
summary
Memory hardware history is framed around concrete constraints and prototypes: commodity vendors used to accept only 0.01% area overhead (0.1% requires ~10x gain, >0.5% was rejected), yet HBM uses ~50% area for TSVs and HBM‑PIM leaves one quarter of die for cells (≈300% overhead). DRAM refresh runs every 64 ms (≈16 full-memory refreshes/sec, ~1% perf cost). Crossbar resistive arrays implement analog GEMV, UPMEM ships DIMMs with 11‑stage in‑order cores plus multithreading, CXL exposes coherent remote memory, and HBM stacks deliver ~7.2 Tb/s and 384 GB in current systems.
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chapters (11)
- 0:00Welcome
- 2:51Modern memory landscape
- 9:58Motivation for memory innovation
- 13:53DDR memory deep dive
- 24:06DDR and GDDR properties
- 34:26High-bandwidth memory
- 43:03Non-volatile memory
- 48:31CXL interconnect scaling
- 52:52Processing in memory
- 1:06:46Memory management challenges
- 1:10:42Q&A
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