Unleashing the Power of RISC-V E-Trace with a Highly Efficient Software Decoder
summary
Siemens EDA presents a software E-Trace decoder that reconstructs full instruction traces from a compressed on‑chip encoder, claiming up to 700x compression and showing a measured 46% reduction in bits per instruction when optional extensions are enabled. Decoding time rises from ~108 ms to ~150 ms across mbench, and CPU work increases from 141 vs 198 cycles/instruction with extensions off versus on. Provides a Python API (four lines to iterate PCs), a CD API for custom instructions (four callbacks), and a Seagate case where trace drove a 3× cycle reduction in a hot kernel.
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chapters (8)
- 0:00Introduction
- 0:43What is trace
- 3:14Hardware and software decoder
- 7:26Compression efficiency
- 8:53Decoder performance
- 11:00API and custom instructions
- 13:29Extensions trade-offs
- 14:36Q&A
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