FGMT-RiscV running on an FPGA evaluation board with a live GDB debug session

on YouTube ↗11m

" summary

A fine‑grained multithreading RISC‑V core runs on a Basis three board in an FPGA with a shared memory and Wishbone peripherals, a timer interrupt and seven‑segment outputs; it uses no program counter register, instead circulating tokens = PC + thread number through one instruction pipeline. The demo boots from flash, maps the GDB serial link as GDB server as thread 0, shows 16 threads demonstrated (configurable to 32/64), WFI-based interrupt handling, and live GDB control of thread start/stop — it works.

AI-written summary · about

" chapters (7)

1. 0:00Introduction to FGMT-RiscV
2. 1:17Interrupt handling in FGMT-RiscV
3. 2:21Debugging and monitoring setup
4. 3:26Demo system overview
5. 4:34Loading and starting software
6. 6:45Live demo begins
7. 10:22Q&A and closing remarks

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