“One Student One Chip" - Learn to Create Your Own RISC-V Processor From Scratch
summary
Third-generation SOC called StarrySky development board integrates multiple student-designed RISC-V cores selectable by a six-bit DIP switch, ships with RT-Thread in SPI flash, and a 4-bit DIP to set clock from 25–350 MHz. A second-year undergraduate completes RTL tape-out (costs covered), writes a RISC-V core, system library, drivers, NanoOS and compiler, flashes Mario and a university emblem, and demonstrates the chip boots and runs the software.
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chapters (4)
- 0:00Introduction to OSOC
- 1:35Technical board details
- 3:02Student project demonstration
- 7:33Philosophy and Q&A
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