RVfpga: Using A Commercial RISC-V Processor to Teac...

on YouTube ↗10m

" summary

A teaching package that targets a commercial RISC‑V SweRV EH1 core to an FPGA and ships labs, guides, and a Vivado/PlatformIO toolflow. Materials show building Chips Alliance’s SweRVolf SoC, programming with Vivado and PlatformIO/VSCode, running on Digilent Nexus A7 or Nexus 4 DDR, adding 7‑segment, SPI/I2C/UART and interrupts, modifying pipeline and caches to add custom instructions, and 20 labs for a 1–2 semester course; demo boots and drives LEDs and seven‑segment displays.

AI-written summary · about

" chapters (11)

1. 0:00Introduction to RVfpga
2. 1:00Hardware and Tools
3. 1:26Swerve Core and SoC
4. 2:39RVfpga Course Materials
5. 3:33Part 1: Labs and Programming
6. 4:26Part 2: I/O and Peripherals
7. 5:09Part 3: Core Analysis
8. 5:44Part 4: Memory Systems
9. 6:14RVfpga System Demo
10. 8:02Conclusion and Roadmap
11. 9:33Registration and Q&A

" related talks

• 02h 18mRISC-V 101kalista Redmond · RISC-V 101 2023
• 02mRISC-V WelcomeKim McMahon · RISC-V Forum: Embedded Technologies 2021
• 10mRISC-V Virtual Platforms for Early RISC-V Embedded Software DevelopmentKevin McDermott, Lee Moore, Hugh O’Keeffe · 8th RISC-V Workshop Barcelona 2018
• 17mDemo: RISC-V Models for Verification, Software Development and Architectural Explor...Larry Lapides · RISC-V Summit 2022
• 37mKeynote: RISC-V Launchpad ShowcaseTiffany Sparks · RISC-V Summit North America 2023
• 37mWhy go RISC-V-y?Ivan Vasilev · HackConf 2021 Online edition
• 14mExtending RISC-V with SCAIE-VTammo Mürmann · ORConf 2025
• 14mUse of RISC-V on Pixel Visual CoreMatt Cockrell · 8th RISC-V Workshop Barcelona 2018