RISC-V True Random Number Generation: Probably Too Important to be Left to Chance
summary
Architecture separates the raw Entropy Source from DRBGs and exposes a single ISA call POLL_ENTROPY that returns 16-bit samples with a status nibble and a minimum requirement of ~8 bits of entropy per sample. A minimal reference Minidice uses ring oscillators, a PLUMS-like conditioner, runtime repetition and adaptive-proportion tests, and is synthesizable on Xilinx 7 and Lattice ECP5 FPGAs driving a picoRV32; final seeding and compression use RISC-V AES instructions into a standard DRBG.
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chapters (11)
- 0:00Introduction to RISC-V DRNG
- 1:37Design specifications
- 4:25Polling for entropy
- 5:55Hardware vs software generation
- 7:13Instruction set architecture
- 8:37Minimal security requirements
- 10:22Interrupts and post-processing
- 12:29Reference implementation
- 13:54Ring oscillators and modeling
- 17:20Physical security and conditioning
- 20:28Techniques and performance
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