RISC-V Spotlight: Expanding the RISC-V Horizon and Beyond
summary
Andes unveils two new cores: x65: 13‑stage, four‑way superscalar RV64 with SV48 and 64KB private L1 caches, claiming ~25% higher frequency/power and >60% CoreMark uplift versus prior 45MP and near‑3x IMPACT benchmark speed, predicted >2x SPEC bandwidth. The x45 MPV: 1024‑bit vector engine with up to 16MB scratch, 8–64KB D$ and “endless streaming pro” bypassing global memory supports RISC‑V V1.0, shows 20–50% gains over x27v, and ships with Andes IDE, optimized compilers, pipeline visualizer, SystemC models and TF‑Lite/TVM toolchain. Company reports 300 customers, 10B+ SoCs shipped.
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chapters (11)
- 0:00Intro
- 2:23Andes Is/Has Driving Innovations
- 4:28AndesCore™ On the Horizon
- 5:40AndesCore AX65: 1st Member of AX60-Series
- 7:15AX65 Microarchitecture: Overview
- 9:08Preliminary Performance Results
- 11:04AX45MPV Core and Multicore Cluster
- 12:59AX45MPV: 1024-bit VPU
- 15:29NX45V (AX45MPV Single Core) vs. NX27V
- 16:16Andes Tools and Software Solutions
- 17:38Expanding RISC-V Beyond the Horizon
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