The New Verification Ecosystem that Supports RISC-V Verification fo...
summary
A configurable imperas DV processor model acts as a cycle-accurate reference for RTL checks while Breker’s test-suite synthesis generates run-ready tests from Core Integrity fast app and SoC Integrity fast app libraries. Tests run on a virtual platform before RTL and reuse identical stimuli for RTL-in-the-loop, exercising multi-core cache-coherency scenarios, custom ISA extensions, and error-injection paths. The flow produces reproducible load/store comparisons, execution profiles, and GUI thread traces to pinpoint mismatches, cutting manual test development and expensive regressions without losing spec compliance.
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chapters (11)
- 0:00Intro
- 0:13The New Verification Ecosystem Supporting RISC-V Verification for all Adopters
- 1:17Verification challenges for RISC-V cores & systems imperas
- 3:10Imperas Environment for Embedded Software Development, Debug & Test
- 4:47Imperas: The RISC-V simulation leader
- 6:13Breker Background: Test Suite Synthesis for RISC-V Cores & SoCs
- 8:43Modular, Configurable, Extendable VIP
- 11:02RISC-V verification challenges addressed by Imperas/Breker work
- 11:33Example Verification Test Note: Simple Test for Fast Demonstration Purposes
- 13:29TrekDebug-Execution Profiling (based on instruction-count)
- 14:07Summary
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