Introduction to RISC-V Processor Verification
summary
Processor verification is roughly five times harder than SoC work, so projects use a mix of post‑simulation trace compare and asynchronous continuous compare with an ISS reference model (Imperas/OVPsim Plus), verification IP that formats RTL traces into the model, SystemVerilog functional coverage, and integration with Synopsys VCS/Verdi and Cadence waveforms for code debug. A predictive engine handles interrupts and debug, CV32E40P has taped out using this flow, more than 100 organizations use OVPsim Plus, and four additional cores are in flight.
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chapters (17)
- 0:00Introduction
- 0:40RISCV disconnect
- 1:40Agenda
- 1:58Verification Plan
- 2:51Hello World
- 4:04Instruction Set Simulator
- 5:01Asynchronous Continuous Compare
- 6:12Block Diagram
- 7:09Reference Model
- 9:19Verification IP
- 10:18VBI
- 10:37Functional Coverage
- 11:30Directed Tests
- 12:23Debug
- 13:00Open Hardware
- 14:02Customers and Partners
- 14:48Conclusion
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