embedded world 2023
2023-03-14..2023-03-16
Nuremberg, Germany
[embedded world 2016, embedded world 2018, Embedded World 2019, embedded world 2021 DIGITAL, embedded world 2022, embedded world 2023]
| title | author | length |
|---|---|---|
| MIPS Interview | 03m | |
MIPS describes the new Evo Core p87 CPU enabling a high‑performance multi‑core, multi‑class “econo” solution and says MobilEye is already using it in an… | ||
| CloudBear Interview | 03m | |
Processor IP company offering RISC‑V CPU IP from tiny MCU cores to higher‑performance cores, claiming a scalable portfolio that targets smart metering, motor… | ||
| Syntacore RISC-V IP | Lisa Yang | 15m |
Company markets a customizable RISC‑V CPU lineup with sscr1 free on GitHub, silicon-proven cores across foundries down to 5 nm, and delivered silicon from MCU… | ||
| ZAYA Interview | 03m | |
Zaya delivers a software stack for RISC-V microcontroller security that implements isolation, access policies and a secure runtime for resource-constrained… | ||
| Ubuntu on RISC-V | Heinrich Schuchardt | 07m |
Ubuntu runs on RISC‑V with 93% of x86 packages already available, language runtimes like Python, Java, Node, Go and C/C++ working, and .NET runtime currently… | ||
| Codeplay Software Interview | 04m | |
About a year after Intel acquires Codeplay the company operates as an Intel-owned subsidiary focused on advancing the SYCL open standard and the oneAPI… | ||
| Tiempo Interview | 03m | |
Announcement of a new secure element IP called physic we for the X5 CPU core that claims not just a CPU but a plug‑and‑play subsystem with crypto accelerators… | ||
| Canonical Interview | 05m | |
Canonical reports 93% of packages already run on RISC‑V and treats RISC‑V as an equal architecture, with Ubuntu Core as the embedded-focused OS using snaps and… | ||
| RISC-V processor IP product line | Alexander Kozlov | 15m |
RISC-V IP lineup targets MCU to application-class SoCs with configurable pipelines and extensions: small 3-stage BM310 32-bit / BM610 64-bit MCUs… | ||
| Getting Started with RISC-V Custom Instructions | Jon Taylor | 11m |
Imperas provides an instruction-accurate simulator and extension libraries that let teams add RISC‑V custom opcodes, profile C code, then recompile and… | ||
| Andes Interview | 05m | |
Andes announces a collaboration with Asus Raspberry Pi form factor board delivering a Linux‑capable, industrial‑grade system for factory automation at lower… | ||
| MachineWare Interview | 03m | |
Sim5 is a fast functional RISC‑V simulator claiming to be the fastest there is, built to run an entire target software stack on every commit so teams can… | ||
| Imperas Interview | 06m | |
Imperas describes concrete work: a RISC‑V Imperas DV processor verification product line with new functional coverage verification IP for measurable… | ||
| RISC-V Android Bring-Up using SIM-V | Lukas Jünger | 11m |
Sim5 claims a 2.5× faster RISC-V functional simulator that completes a full Android boot (about 100 billion instructions) and runs Android 12 images while… | ||
| Green Hills Software Interview | 04m | |
Tools and compilers for RISC-V compilers since 2018 expand into real-time OS capabilities and now target hypervisor support for RISC-V, aiming to move… | ||
| A First Secure RISC-V Common Criteria Certified Root of Trust | Serge Maginot | 17m |
Announces an integrated secure enclave IP built around RISC‑V Ibex core with crypto accelerators, TRNG, sensors and active shield, delivered as soft IP or… | ||
| Why RISC-V is Inevitable | Andy Moore | 13m |
RISC-V claims real traction: over 10 billion cores shipped with Qualcomm reporting 650 million cores and SiFive and others delivering embedded to datacenter… | ||
| RISC-V CPUs for the New Era of Heterogeneous Computing | Srinivas Kantheti | 15m |
MIPS presents a RISC‑V platform built into an Evo core P8700 (out‑of‑order, 16‑stage pipeline, up to 2 GHz) plus the simpler I8500, with a coherency manager… | ||
| Early RISC-V Software Verification with SIM-V | Lukas Jünger | 13m |
A fast functional RISC‑V simulator claims 2.5× faster execution than state‑of‑the‑art solutions, runs full Linux systems and exposes the PMU so perf returns… | ||
| Certified Security and Containerisation for RISC-V Microcontrollers | Murat Cakmak | 15m |
A minimal PSA-certified TEE for MMU-less RISC-V cores (Zaya) exposes the standard PSA crypto API, uses available hardware virtualization, and runs as an… | ||
| oneAPI with SYCL gives Software Portability including Nvidia | Charles Macfarlane | 18m |
OneAPI uses SYCL as a single-source C++ standard and offers 90% automated conversion from CUDA via the dpct / open-source cyclomatic tool, with the remaining… | ||
| Powering Up RISC-V Excellent, Secure and Maintainable Software | Steve Barriault | 14m |
Canonical ports Ubuntu Core to RISC‑V with 93% package coverage across supported boards, packaging apps as snap (squashfs) bundles, enabling transactional OTA… | ||
| Enabling Production Program Software Development for RISC-V | Dan Mender | 10m |
Toolchain and OS suite targets production RISC‑V programs with standalone compilers and debuggers (32/64‑bit, custom instructions), a MULTI IDE that debugs… | ||
| A Peek Inside a New RISC-V CPU for Autonomous Vehicles | Itai Yarom | 12m |
MIPS announces a RISC-V CPU family aimed at ADAS and autonomous stack with a 60-stage out-of-order pipeline, multi-cluster multicore multithreading and a… | ||
| Why RISC-V is Inevitable | Calista Redmond | 20m |
Claims RISC‑V is already mainstream: 10+ billion cores in market with Qualcomm reporting 650 million cores, Intel committing a billion‑dollar push, and Alibaba… | ||
| Introduction to RISC-V Processor Verification | Larry Lapides | 16m |
Processor verification is roughly five times harder than SoC work, so projects use a mix of post‑simulation trace compare and asynchronous continuous compare… | ||
| Expanding the RISC-V Horizon and Beyond | Florian Wohlrab | 20m |
Andes reports 17 years in business, over 300 commercial licenses and 10 billion cores shipped, with shipments rising from 1B (2018) to 3B (2021). Product… | ||
| RISC-V | 02m | |
Claims RISC-V is inevitable and a global connective movement, positioned as the foundation for automotive SoCs and edge devices; asserts more than 10 billion… | ||
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