A Peek Inside a New RISC-V CPU for Autonomous Vehicles
summary
MIPS announces a RISC-V CPU family aimed at ADAS and autonomous stack with a 60-stage out-of-order pipeline, multi-cluster multicore multithreading and a shared-memory CPU–AI fabric to move sensor data without software copies. It adds user-defined RISC-V prefetch/snoop ops to close memory gaps, supports RTOS and Linux with full MMU/virtualization, claims roughly 70% presence in existing ADAS domains, and says silicon and OEM licensing rollouts happen next year.
AI-written summary · about
chapters (7)
- 0:00Introduction to RISC-V in automotive
- 1:47RISC-V adoption in ADAS systems
- 3:12MIPS transition to RISC-V
- 5:43CPU architecture details
- 7:56Memory and performance optimization
- 9:19Safety and deployment experience
- 10:21Summary and ecosystem benefits
related talks
28mRISC-V FutureWatch: MIPS - Bringing a New Level of Scalability to RISC-V - MIPS eVoco...
53mWhat’s the Reality of RISC-V in Automotive?
11mKeynote: Shaping the Future of Automotive Computing with RISC-V
17mKeynote: Racing to Adoption: From Momentum to Mainstream with RISC-V
19mAccelerating Edge AI with the Help of RISC-V
20mCould RISC-V Become a Force in HPC?
16mAutomotive Solution Empowered by RISC-V Based Security and Functional Safety Module
20mIntegrate RISC V to build Open Common Automotive Platform