Lightning Talk: Design Verification with Step-and-Compare for RISC-V...

on YouTube ↗09m

" summary

Uses an asynchronous lockstep compare against an architectural “envelope” model that covers drafts and extensions, exporting GPRs FPRs CSRs and the vector register bank for scoreboard checks. Provides a RISC‑V Verification Interface with SystemVerilog/SystemC hooks, runs directed, random and compliance suites even when only a standalone coprocessor exists (OVI/Core5 XAF wrap), and demonstrates RVV v0.7.1 with ELEN 64 VLEN 2048 SLEN 2048 showing waveform-driven state agreement.

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" chapters (11)

1. 0:00Intro
2. 0:35Model Abstractions
3. 1:34Types of Comparison
4. 2:04Requirements of a Reference
5. 3:18RISC-V Vector Extension Configuration Options
6. 4:00Verification of Processor Inclusive Extensions RTL and Reference Model (RM) Step/Compare
7. 4:54RVVI (RISC-V Verification Interface)
8. 5:38Testbench Standard Interfaces imperas
9. 5:54Verification of Co-Processor
10. 7:22Demo
11. 8:44Conclusions

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