Lightning Talk: Using Embedded FPGAs for Custom Vector Extensions
summary
The talk describes using the open-source FABulous framework to integrate embedded FPGA (eFPGA) regions into a RISC-V core (e.g., FlexBex) to implement custom vector extensions. It explains applying eFPGA reconfigurability for ML vector processing—supporting custom data types (small integers), non-linear arithmetic, and operations on compressed data formats as custom instructions inside the CPU.
AI-written summary · about
chapters (6)
- 0:00Start
- 0:05Using Embedded FPGAs for Custom Vector Extensions
- 3:24Tightly Coupled Reconfigurable Instructions
- 5:37Custom Interlay Examples - Crypto • AES, DES, SHA, Montgomery multiplication, TRNG
- 7:06Contributors
- 8:21Chip Implementations
related talks
11mLightning Talk: The CFU: Custom Hardware with RISCV and Zephyr
24mUniversal Tools for Acceleration, Timing, Integration & Machine Enhancement
15mA Sneak Preview into the FABulous 2.0 eFPGA Framework
30mCFU Playground: Model-specific Acceleration on FPGAs
19mEnhancing RISC-V Embedded Processor Performance Through Advanced Instruction F...
09mDeveloping Custom RISC-V ISA Extensions for General Embedded Image Processing Operations
43mSoftware Development Trends for FPGAs
20mBoosting AI on Semidynamics RISC-V Cores with Custom Tensor Instr...