A Sneak Preview into the FABulous 2.0 eFPGA Framework
summary
FABulous 2.0 shows concrete upgrades: direct one-click Libra lane → GDS for optimized tiled fabric integration, automated timing-model extraction from ASIC flow for nextpnr, and automated custom-tile and IO generation that turns primitives into placed-and-routed tiles. A real chip from a Google MPW (images in block RAM and readout electronics implemented on fabric) runs entirely on open-source flows using nextpnr/GHDL. Fabric supports partial reconfiguration, and the framework is silicon proven (>10 manufactured chips, 28–180 nm; 22 nm in progress).
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chapters (9)
- 0:00Introduction
- 1:08What is Fabulous
- 2:14Batteries included features
- 3:39Fabric generation flow
- 4:42Version 2.0 improvements
- 6:10Automated testing evolution
- 7:18Live demo
- 10:31Summer school hackathon
- 11:13Q&A
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